In a multi chip package (MCP) used in a memory card or a solid state drive (SSD), memory chips such as NAND memories are stacked to increase a data storage capacity. The number of memory chips connected per one channel increases. In other words, a plurality of output buffers for outputting data stored in the memory chips to the outside of the memory chips are connected to each of channels in parallel.
Therefore, a load capacitance applied to output buffers of the memory chips increases. When an output circuit for transitioning a signal from a ground level to a power supply level at full amplitude between power supply potentials is adopted, in some case, deterioration in a readout waveform in which the signal falls before sufficiently rising (so-called inter symbol interference (ISI)) occurs and wrong readout is caused. As a method for coping with such a problem, there is a method of increasing the size of the output buffers and increasing a driving ability of the output buffers.
For example, Japanese Patent Application Laid-Open No. 2005-341582 discloses a method of controlling timing of activation of a sampling clock signal in response to a phase of a signal over-sampled in response to a variable equalizing control signal to sufficiently compensate for a timing error and a voltage error caused by the inter symbol interference.
However, when the size of the output buffers is increased, because parasitic capacitance of the output buffers also increases, the load capacity applied to the output buffers of the memory chips further increases. As a result, it is impossible to sufficiently cope with the wrong readout.